LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.dec_pkg.all;

entity ram_a is
port(		clock1 	:in std_ulogic;
			reset1  	:in std_ulogic;
			write1  	:in std_ulogic;
			read1   	:in std_ulogic;
			en1     	:in std_ulogic;
			data1   	:in word16;
			addr1   	:in std_ulogic_vector(8 downto 0);
			clock2  	:in std_ulogic;
			reset2  	:in std_ulogic;
			write2  	:in std_ulogic;
			read2   	:in std_ulogic;
			en2     	:in std_ulogic;
			data2   	:out word16;
			addr2   	:in std_ulogic_vector(8 downto 0)
			);
end ram_a;

ARCHITECTURE beh OF ram_a IS
component rd512x16mux4 is port 
	( 
	QA: out std_logic_vector(15 downto 0);
	QB: out std_logic_vector(15 downto 0);
	CLKA: in std_logic;
	CENA: in std_logic;
	WENA: in std_logic;
	AA: in std_logic_vector(8 downto 0);
	DA: in std_logic_vector(15 downto 0);
	CLKB: in std_logic;
	CENB: in std_logic;
	WENB: in std_logic;
	AB: in std_logic_vector(8 downto 0);
	DB: in std_logic_vector(15 downto 0)
    );
end component;
signal cena ,wena,cenb,wenb:std_logic;
signal da,db,qa,qb :std_logic_vector(15 downto 0);
signal aa , ab:std_logic_vector(8 downto 0);
begin
   cena <= not en1 ;
   wena <= not write1 ;
   da <= std_logic_vector(data1);
   cenb <= not en2 ;
   wenb <= read2;
   db <= (others => '0');
   aa <= std_logic_vector(addr1);
   ab <= std_logic_vector(addr2);
   data2 <= std_ulogic_vector(qb);
  u1:rd512x16mux4 port map
  (
      qb => qb ,
      clka => clock1 ,
      cena => cena,
      wena => wena,
      aa => aa,
      da => da,
      clkb => clock2,
      cenb => cenb,
      wenb => wenb,
      ab => ab,
      db => db
      
     
  );

end Beh;
